With switched-mode power supplies (SMPSs) moving to higher output power and smaller output voltages, the need for multi-phase power converters is continuously growing. With an increasing number of phases, the benefits of a control loop bandwidth closer to or even higher than the switching frequency of the individual phases are well-acknowledged. As simple digital pulse width modulators (DPWMs) are still used in current multi-phase designs, these tend to be one of the limiting factors of the loop bandwidth, and hence the need for improved “smart” DPWMs is clearly evident. Additionally, most of the existing architectures are not able to drive a varying number of phases which is required in systems with phase shedding operation.
Standard multi-phase power converters typically comprise of N phases, use N conventional DPWM modulators to generate the control signals for the power stage switches. Synchronisation between the individual modulators ensures proper phase shift. Naturally sampled DPWMs update the duty cycle once per switching cycle, which allows the update of the inputs of the modulator up to N-times the phase switching frequency. However, each individual DPWM is only updated once per cycle leading to additional problems such as current mismatch during load transients. Most designs overcome these issues by limiting the loop bandwidth, and thereby compromising the system performance.
For single phase applications, this issue has been addressed using several different concepts, such as charged-balanced control, linear-non-linear control, and multi-sampled DPWMs. However to date, these concepts have not been applied to multi-phase applications. As a consequence, multi-phase converters are still driven by standard multi-phase modulators.
A modulation output of a four-phase MP-DPWM is shown in FIG. 1. For each subcycle (Latin numbering), the duty cycle (values shown below the waveform) is applied to the currently active DPWM. While the system respects the number of allowed switching operations per cycle intrinsically, the delay in the application of the duty cycle and the resulting distribution of the output signal is not satisfactory. For the given example, the phases zero and three would take most of the transient current leading to a large current mismatch immediately after the transient. The delay between the reception of the duty cycle command and the application to the power stage can be up to one full DPWM cycle.
U.S. 2008/0310200 describes a multi-phase modulator, in which a decoder and a selector determine first, second, ad third sets of the multiple phases to place in first, second, and third states based on a digital input command. The input signal is split into MSBs and LSBs in an approach which could be referred to as static decoding.
PCT Patent publication number WO2009/076540, Primarion Corp, discloses a multiphase power regulator that operates in conjunction with an active transient response (ATR) system for applying a correction signal to a multiphase pulse width modulator. In the event of a transient, the ATR system may adjust the output of the pulse width modulator to quickly respond to load requirements. The output may be modified by adding pulses, blanking pulses, advancing pulses, and scaling pulses to one or more phases.
U.S. Patent publication number U.S. 2007/109825, Weihong et al, discloses an adaptive pulse positioning system for a voltage converter providing an output voltage, the system including a PWM generation circuit, a sensor, and a pulse positioning circuit. The PWM generation circuit generates a PWM signal with PWM pulses for controlling the output voltage of the voltage controller. The sensor senses an output load condition of the voltage converter and provides a load signal indicative thereof. The pulse positioning circuit adaptively positions the PWM pulses based on the load signal.
U.S. Patent publication number U.S. 2007/262802, Doug et al, discloses a voltage regulator for microelectronic devices using dual edge pulse width modulated control signal. In one example a first digital duty cycle value is received from a voltage controller and a pulse width modulated waveform is generated in response to the first duty cycle value, the waveform comprising of a plurality of pulses with a modulated width. The waveform is applied to a voltage generator to generate a supply of power at a voltage determined by the duty cycle of the waveform. A second digital duty cycle value is received from the controller, and the leading edge of a subsequent pulse of the waveform is advanced if the second digital duty cycle value is greater than the first digital duty cycle. The trailing edge of the subsequent pulse of the waveform is advanced if the second digital duty cycle value is less than the first digital duty cycle value.
The invention is directed towards providing an improved multi-phase digital pulse width modulator.